| 8051
special function registers (SFRs)
|
| Symbol |
Name |
Address |
Contents after
reset |
| ACC* |
Accumulator |
0E0H |
00000000 |
| B* |
B
register |
0F0H |
00000000 |
| PSW* |
Program
Status Word |
0D0H |
00000000 |
| SP |
Stack
Pointer |
81H |
00000111 |
| DPTR |
Data
Pointer 2 bytes |
|
|
| DPL |
Data
Pointer low byte |
82H |
00000000 |
| DPH |
Data
Pointer high byte |
83H |
00000000 |
| P0* |
Port 0 |
80H |
11111111 |
| P1* |
Port 1 |
90H |
11111111 |
| P2* |
Port 2 |
0A0H |
11111111 |
| P3* |
Port 3 |
0B0H |
11111111 |
| IP* |
Interrupt
Priority Control |
0B8H |
XXX00000 |
| IE* |
Interrupt
Enable Control |
0A8H |
0XX00000 |
| TMOD |
Timer/Counter
Mode Control |
89H |
00000000 |
| TCON* |
Timer/Counter
Control |
88H |
00000000 |
| TH0 |
Timer/Counter
0 high byte |
8CH |
00000000 |
| TL0 |
Timer/Counter
0 low byte |
8AH |
00000000 |
| TH1 |
Timer/Counter
1 high byte |
8DH |
00000000 |
| TL1 |
Timer/Counter
1 low byte |
8BH |
00000000 |
| SCON* |
Serial
Control |
98H |
00000000 |
| SBUF |
Serial
Data Buffer |
99H |
Indeterminate |
| PCON |
Power
Control |
87H |
0XXXXXXX |
| (*
= bit addressable) 
 functional descriptions
PSW: Program Status Word (bit addressable)
(msb) |CY|AC|F0|RS1|RS0|OV|-|P| (lsb) |
| Symbol |
Position |
Name
& Significance |
| CY |
PSW.7 |
Carry
flag. |
| AC |
PSW.6 |
Auxiliary
Carry flag. |
| F0 |
PSW.5 |
Flag 0
available to the user for general purpose. |
| RS1 |
PSW.4 |
Register
Bank select bit 1. (see note) |
| RS0 |
PSW.3 |
Register
Bank select bit 0. (see note) |
| OV |
PSW.2 |
Overflow
flag. |
| - |
PSW.1 |
User
definable flag. |
| P |
PSW.0 |
Parity
flag. Set/cleared by hardware to each instruction cycle to indicate an odd/even number of
"one" bits in the Accumulator. |
| NOTE: |
| RS1 |
RS0 |
REGISTER
BANK |
ADDRESS |
| 0 |
0 |
0 |
00H-07H |
| 0 |
1 |
1 |
08H-0FH |
| 1 |
0 |
2 |
10H-17H |
| 1 |
1 |
3 |
18H-1FH |
PCON: Power Control Register (not bit addressable)
(msb) |SMOD|-|-|-|GF1|GF0|PD|IDL| (lsb) |
| Symbol |
Position |
Name
& Significance |
| SMOD |
PCON.7 |
Double
baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is
doubled when the serial port is used in modes 1, 2, or 3. |
| - |
PCON.6 |
Not
implemented |
| - |
PCON.5 |
Not
implemented |
| - |
PCON.4 |
Not
implemented |
| GF1 |
PCON.3 |
General-purpose
flag bit. |
| GF0 |
PCON.2 |
General-purpose
flag bit. |
| PD |
PCON.1 |
Power
Down bit. Setting this bit activates the Power Down operation in the 8051BH. (Available
only in CHMOS). |
| IDL |
PCON.0 |
Idle
Mode bit. Setting this bit activates Idle Mode operation in the 8051BH. (Available only in
CHMOS). |
IE: Interrupt Enable Register (bit addressable)
If the bit is 0, the corresponding interrupt is
disabled. If the bit is 1, the corresponding interrupt is enabled.
(msb) |EA|-|ET2|ES|ET1|EX1|ET0|EX0| (lsb) |
| Symbol |
Position |
Name
& Significance |
| EA |
IE.7 |
Disables
all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit. |
| - |
IE.6 |
Not
implemented. |
| ET2 |
IE.5 |
Enable/disable
Timer 2 overflow or capture interrupt. (8052 only). |
| ES |
IE.4 |
Enable/disable
serial port interrupt. |
| ET1 |
IE.3 |
Enable/disable
Timer 1 overflow interrupt. |
| EX1 |
IE.2 |
Enable/disable
external interrupt 1. |
| ET0 |
IE.1 |
Enable/disable
Timer 0 overflow interrupt. |
| EX0 |
IE.0 |
Enable/disable
external interrupt 0. |
|
| INTERRUPT
SOURCE |
VECTOR
ADDRESS |
| IE0 |
0003H |
| TF0 |
000BH |
| IE1 |
0013H |
| TF1 |
001BH |
| RI
& TI |
0023H |
| TF2
& EXF2 (8052 only) |
002BH |
IP: Interrupt Priority Register (bit addressable)
If the bit is 0, the corresponding interrupt has a
lower priority and if the bit is 1, the corresponding interrupt has a higher priority.
(msb) |-|-|PT2|PS|PT1|PX1|PT0|PX0| (lsb) |
| Symbol |
Position |
Name
& Significance |
| - |
IP.7 |
Not
implemented. |
| - |
IP.6 |
Not
implemented. |
| PT2 |
IP.5 |
Defines
the Timer 2 interrupt priority level (8052 only). |
| PS |
IP.4 |
Defines
the serial port interrupt priority level. |
| PT1 |
IP.3 |
Defines
Timer 1 interrupt priority level. |
| PX1 |
IP.2 |
Defines
External interrupt 1 priority level. |
| PT0 |
IP.1 |
Defines
Timer 0 interrupt priority level. |
| PX0 |
IP.0 |
Defines
External interrupt 0 priority level. |
TCON: Timer/Counter Control Register (bit addressable)
(msb) |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| |
| Symbol |
Position |
Name
& Significance |
| TF1 |
TCON.7 |
Timer 1
overflow flag. Set by hardware when Timer/Counter 1 overflows. Cleared by hardware as
processor vectors to the interrupt service routine. |
| TR1 |
TCON.6 |
Timer 1
run control bit. Set/cleared by software to turn Timer/Counter 1 On/Off. |
| TF0 |
TCON.5 |
Timer 0
overflow flag. Set by hardware when Timer/Counter 0 overflows. Cleared by hardware as
processor vectors to the interrupt service routine. |
| TR0 |
TCON.4 |
Timer 0
run control bit. Set/cleared by software to turn Timer/Counter 0 On/Off. |
| IE1 |
TCON.3 |
External
Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected. Cleared
by hardware when interrupt is processed. |
| IT0 |
TCON.2 |
Interrupt
1 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts. |
| IE0 |
TCON.1 |
External
Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected. Cleared
by hardware when interrupt is processed. |
| IT0 |
TCON.0 |
Interrupt
0 type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts. |
TMOD: Timer/Counter
Mode Control Register (not bit addressable)
(msb) timer1> |GATE|C/T|M1|M0|
timer0> |GATE|C/T|M1|M0| (lsb) |
| Symbol |
Name
& Significance |
| GATE |
When
TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software
control). |
| C/T |
Timer
or Counter selector. Cleared for Timer operation (input from internal system clock). Set
for counter operation (input from Tx input pin). |
| M1 |
Mode
selector bit. (see note) |
| M0 |
Mode
selector bit. (see note) |
| NOTE: |
| M1 |
M0 |
OPERATING
MODE |
| 0 |
0 |
0,
13-bit Timer (MCS-48 compatible). |
| 0 |
1 |
1,
16-bit Timer/counter. |
| 1 |
0 |
2, 8-bit
Auto-Reload timer/counter. |
| 1 |
1 |
3,
(Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits,
TH0 is an 8-bit timer and controlled by Timer 1 control bits. |
| 1 |
1 |
3,
(Timer 1) Timer/counter 1 stopped. |
SCON: Serial Port Control Register (bit addressable)
(msb) |SM0|SM1|SM2|REN|TB8|RB8|TI|RI| (lsb) |
| Symbol |
Position |
Name
& Significance |
| SM0 |
SCON.7 |
Serial
Port mode select. (see note 1) |
| SM1 |
SCON.6 |
Serial
Port mode select. (see note 1) |
| SM2 |
SCON.5 |
Enables
the multiprocessor communications features in modes 2 & 3. In mode 2 or 3, if SM2 is
set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1,
if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0,
SM2 should be 0. (see note 2) |
| REN |
SCON.4 |
Set/cleared
by software to enable/disable reception. |
| TB8 |
SCON.3 |
The 9th
bit that will be transmitted in modes 2 & 3. Set/cleared by software. |
| RB8 |
SCON.2 |
In
modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the
stop bit that was received. In mode 0, RB8 is not used. |
| TI |
SCON.1 |
Transmit
interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software. |
| RI |
SCON.0 |
Receive
interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by
software. |
| NOTE 1: |
| SM0 |
SM1 |
MODE |
DESCRIPTION |
BAUD
RATE |
| 0 |
0 |
0 |
Shift
Register |
Fosc./12 |
| 0 |
1 |
1 |
8-bit
UART |
Variable |
| 1 |
0 |
2 |
9-bit
UART |
Fosc./64
OR Fosc./32 |
| 1 |
1 |
3 |
9-bit
UART |
Variable |
|
|
|
|
|
| NOTE 2: SERIAL PORT SET-UP |
| Mode |
SCON |
SM2
Variation |
| 0 |
10H |
Single
Processor environment (SM2 = 0) |
| 1 |
50H |
Single
Processor environment (SM2 = 0) |
| 2 |
90H |
Single
Processor environment (SM2 = 0) |
| 3 |
D0H |
Single
Processor environment (SM2 = 0) |
| 0 |
NA |
Multiprocessor
environment (SM2 = 1) |
| 1 |
70H |
Multiprocessor
environment (SM2 = 1) |
| 2 |
B0H |
Multiprocessor
environment (SM2 = 1) |
| 3 |
F0H |
Multiprocessor
environment (SM2 = 1) |
Alternate Functions
of Port 3 (bit addressable)
(msb) |RD|WR|T1|T0|INT1|INT0|TXD|RXD| (lsb) |
| Symbol |
Position |
Name
& Significance |
| RD |
P3.7 |
External
Data Memory read strobe. |
| WR |
P3.6 |
External
Data Memory write strobe. |
| T1 |
P3.5 |
Timer/counter
1 external input. |
| T0 |
P3.4 |
Timer/counter
0 external input. |
| INT1 |
P3.3 |
External
interrupt 1. |
| INT0 |
P3.2 |
External
interrupt 0. |
| TXD |
P3.1 |
Serial
output port. |
| RXD |
P3.0 |
Serial
input port. |
